101 Jobs für Coding Languages
Stellenangebote Coding Languages Jobs
Job vor 2 Tagen bei Neuvoo gefunden
Delivery Hero
• Berlin
Führungs-/ Leitungspositionen
Sabbaticals
[. .. ] highly complex, or distributed organizations. Cloud-Native Architecture: Deep familiarity with cloud-native microservice landscapes, event-driven architectures, and robust containerization/ observability frameworks. Tooling Language Expertise: Technical proficiency in modern [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] coding languages (such as Go) and robust experience with AWS and GCP infrastructure ecosystems. Leadership Experience: Senior Leadership Track Record: 5+ years in senior engineering leadership roles (Director level or above) with demonstrated success managing multiple teams of teams and serving internal customers. Strategic Influencer: Outstanding communication and influencing skills, with a [. .. ]
Job gestern bei StepStone gefunden
Bosch Gruppe
PhD-Agentic AI for ASIC Development Acceleration
• Dresden
Work-Life-Balance
[. .. ] independent working style Experience Expertise: Fundamental experience in the use of AI tools, agent development and prompting is mandatory Strong expertise in Python scripting, general understanding in [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] VHDL, Verilog and coding as well as efficient handling of various data formats is a must Basic understanding of ASIC design methodologies in digital design, analog/ mixed signal simulation and wafer testing Familiarity with AI platform specific pros and cons to deploy them for the identified use-cases Experience in software development is a plus Languages: Proficient English is a must; advanced German language skills are beneficial Education: A degree (Diploma/ M. Sc. ) in electrical engineering, computer science or an equivalent field with outstanding academic results is required We offer you an inspiring and challenging environment in which to successfully complete your Ph D within a [. .. ]
Job vor 10 Tagen bei Jobware gefunden
Advantest Europe GmbH
• 71034, 71032, Böblingen
Teilzeit
[. .. ] keep power consumption under control, solve challenging technical problems, and deliver high quality results on schedule and at scale. Job Duties Responsibilities Architecture development for CMOS designs [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/ cases generation. Documentation of implemented functionality Constraint generation and synthesis of IP blocks and the chip top level Analysis of timing and power consumption Support for floor-planning and physical design Close collaboration with design [. .. ] cycle Experience in Register Transfer Level (RTL) coding (Verilog and System Verilog) Experience with standard simulation tools for digital designs Basic knowledge about UNIX or Linux environment and using programming languages Technical communication, team work and problem solving skills English language skills Our offer Flexibility Benefits Development Fitness Security Flexible and trust-based working hours, 30 vacation days + option for additional vacation days, mobile working, individual part-time models and programs for extended periods of absence Attractive salary, share in Advantests [. .. ]
Job am 08.04.2026 bei JobMESH gefunden
Advantest Europe GmbH
Expert Digital ASIC Design Engineer (m/f/d)
• Baden- Wurttemberg Böblingen
[. .. ] problems, and deliver high quality results on schedule and at scale. Job Duties Responsibilities Requirements gathering and elicitation for devices and IP Architecture development for CMOS designs [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/ cases generation. Documentation of architecture and implemented functionality Support for floor-planning and physical design Mentoring Junior Engineers Collaboration with other functions Your Qualifications University degree, Diploma or BS EE Expert background in digital design [. .. ] and silicon development cycle Experience in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs Basic knowledge about UNIX or Linux environment and using programming languages Technical communication, team work and problem solving skills English language skills Our offer Flexibility Benefits Development Fitness Security Flexible and trust-based working hours, 30 vacation days + option for additional vacation days, mobile working, individual part-time models and programs for extended periods of absence Attractive salary, share in [. .. ]
Job am 08.04.2026 bei JobMESH gefunden
Advantest Europe GmbH
Senior Digital ASIC Design Engineer Synthesis (m/f/d)
• Baden- Wurttemberg Böblingen
[. .. ] keep power consumption under control, solve challenging technical problems, and deliver high quality results on schedule and at scale. Job Duties Responsibilities Architecture development for CMOS designs [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/ cases generation. Documentation of implemented functionality Constraint generation and synthesis of IP blocks and the chip top level Analysis of timing and power consumption Support for floor-planning and physical design Close collaboration with design [. .. ] cycle Experience in Register Transfer Level (RTL) coding (Verilog and System Verilog) Experience with standard simulation tools for digital designs Basic knowledge about UNIX or Linux environment and using programming languages Technical communication, team work and problem solving skills English language skills Our offer Flexibility Benefits Development Fitness Security Flexible and trust-based working hours, 30 vacation days + option for additional vacation days, mobile working, individual part-time models and programs for extended periods of absence Attractive salary, share in [. .. ]
Job am 02.04.2026 bei JobMESH gefunden
Advantest Europe GmbH
Senior Digital ASIC Design Engineer (m/f/d)
• Baden- Wurttemberg Böblingen
[. .. ] technical problems, and deliver high quality results on schedule and at scale. Job Duties Responsibilities Requirements gathering and elicitation for IP Architecture development for CMOS IP designs [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/ cases generation. Documentation of implemented functionality Support for floor-planning and physical design Collaboration with other functions Your Qualifications University degree, Diploma or BS EE Background in digital design (SOC) , Application Specific Integrated Circuit [. .. ] and silicon development cycle Experience in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs Basic knowledge about UNIX or Linux environment and using programming languages Technical communication, team work and problem solving skills English language skills Our offer Flexibility Benefits Development Fitness Security Flexible and trust-based working hours, 30 vacation days + option for additional vacation days, mobile working, individual part-time models and programs for extended periods of absence Attractive salary, share in [. .. ]
Job am 01.04.2026 bei JobMESH gefunden
Advantest Europe GmbH
• Baden- Wurttemberg Böblingen
[. .. ] challenging technical problems, and deliver high quality results on schedule and at scale. Job Duties Responsibilities Requirements gathering and elicitation for IP Architecture development for CMOS designs [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/ cases generation with a focus on chip level Documentation of implemented functionality Support for verification methodology Collaboration with other functions Your Qualifications University degree, Diploma or BS EE Background in digital design (SOC) , ASIC [. .. ] (RTL) coding (Verilog and System-Verilog) Experience with verification methodologies and concepts Experience with standard simulation tools for digital designs Basic knowledge about UNIX or Linux environment and using programming languages Technical communication, team work and problem solving skills English language skills Our offer Flexibility Benefits Development Fitness Security Flexible and trust-based working hours, 30 vacation days + option for additional vacation days, mobile working, individual part-time models and programs for extended periods of absence Attractive salary, share in [. .. ]
Job am 17.06.2026 bei Neuvoo.com gefunden
Advantest Europe GmbH
Senior Digital ASIC Design Engineer (m/f/d)
• Baden- Württemberg Böblingen
[. .. ] technical problems, and deliver high quality results on schedule and at scale. Job Duties Responsibilities Requirements gathering and elicitation for IP Architecture development for CMOS IP designs [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/ cases generation. Documentation of implemented functionality Support for floor-planning and physical design Collaboration with other functions Your Qualifications University degree, Diploma or BS EE Background in digital design (SOC) , Application Specific Integrated Circuit [. .. ] and silicon development cycle Experience in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs Basic knowledge about UNIX or Linux environment and using programming languages Technical communication, team work and problem solving skills English language skills Our offer Flexibility Benefits Development Fitness Security Flexible and trust-based working hours, 30 vacation days + option for additional vacation days, mobile working, individual part-time models and programs for extended periods of absence Attractive salary, share in Advantests [. .. ]
Job am 17.06.2026 bei Neuvoo.com gefunden
Advantest Europe GmbH
• Baden- Württemberg Böblingen
[. .. ] keep power consumption under control, solve challenging technical problems, and deliver high quality results on schedule and at scale. Job Duties Responsibilities Architecture development for CMOS designs [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/ cases generation. Documentation of implemented functionality Constraint generation and synthesis of IP blocks and the chip top level Analysis of timing and power consumption Support for floor-planning and physical design Close collaboration with design [. .. ] cycle Experience in Register Transfer Level (RTL) coding (Verilog and System Verilog) Experience with standard simulation tools for digital designs Basic knowledge about UNIX or Linux environment and using programming languages Technical communication, team work and problem solving skills English language skills Our offer Flexibility Benefits Development Fitness Security Flexible and trust-based working hours, 30 vacation days + option for additional vacation days, mobile working, individual part-time models and programs for extended periods of absence Attractive salary, share in Advantests [. .. ]
Job am 17.06.2026 bei Neuvoo.com gefunden
Advantest Europe GmbH
Senior Digital ASIC Design Engineer Verification (m/f/d) gesucht
• Baden- Württemberg Böblingen
[. .. ] challenging technical problems, and deliver high quality results on schedule and at scale. Job Duties Responsibilities Requirements gathering and elicitation for IP Architecture development for CMOS designs [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/ cases generation with a focus on chip level Documentation of implemented functionality Support for verification methodology Collaboration with other functions Your Qualifications University degree, Diploma or BS EE Background in digital design (SOC) , ASIC [. .. ] (RTL) coding (Verilog and System-Verilog) Experience with verification methodologies and concepts Experience with standard simulation tools for digital designs Basic knowledge about UNIX or Linux environment and using programming languages Technical communication, team work and problem solving skills English language skills Our offer Flexibility Benefits Development Fitness Security Flexible and trust-based working hours, 30 vacation days + option for additional vacation days, mobile working, individual part-time models and programs for extended periods of absence Attractive salary, share in Advantests [. .. ]
Job am 17.06.2026 bei Neuvoo.com gefunden
Advantest Europe GmbH
• Baden- Württemberg Böblingen
[. .. ] problems, and deliver high quality results on schedule and at scale. Job Duties Responsibilities Requirements gathering and elicitation for devices and IP Architecture development for CMOS designs [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/ cases generation. Documentation of architecture and implemented functionality Support for floor-planning and physical design Mentoring Junior Engineers Collaboration with other functions Your Qualifications University degree, Diploma or BS EE Expert background in digital design [. .. ] and silicon development cycle Experience in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs Basic knowledge about UNIX or Linux environment and using programming languages Technical communication, team work and problem solving skills English language skills Our offer Flexibility Benefits Development Fitness Security Flexible and trust-based working hours, 30 vacation days + option for additional vacation days, mobile working, individual part-time models and programs for extended periods of absence Attractive salary, share in Advantests [. .. ]
Job am 17.06.2026 bei Neuvoo.com gefunden
Advantest Europe GmbH
Senior Digital ASIC Design Engineer Synthesis (m/f/d) - Advantest Europe GmbH
• Baden- Württemberg Böblingen
[. .. ] keep power consumption under control, solve challenging technical problems, and deliver high quality results on schedule and at scale. Job Duties Responsibilities Architecture development for CMOS designs [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/ cases generation. Documentation of implemented functionality Constraint generation and synthesis of IP blocks and the chip top level Analysis of timing and power consumption Support for floor-planning and physical design Close collaboration with design [. .. ] cycle Experience in Register Transfer Level (RTL) coding (Verilog and System Verilog) Experience with standard simulation tools for digital designs Basic knowledge about UNIX or Linux environment and using programming languages Technical communication, team work and problem solving skills English language skills Our offer Flexibility Benefits Development Fitness Security Flexible and trust-based working hours, 30 vacation days + option for additional vacation days, mobile working, individual part-time models and programs for extended periods of absence Attractive salary, share in Advantests [. .. ]
Job am 17.06.2026 bei Neuvoo.com gefunden
Advantest Europe GmbH
• Baden- Württemberg Böblingen
[. .. ] technical problems, and deliver high quality results on schedule and at scale. Job Duties Responsibilities Requirements gathering and elicitation for IP Architecture development for CMOS IP designs [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/ cases generation. Documentation of implemented functionality Support for floor-planning and physical design Collaboration with other functions Your Qualifications University degree, Diploma or BS EE Background in digital design (SOC) , Application Specific Integrated Circuit [. .. ] and silicon development cycle Experience in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs Basic knowledge about UNIX or Linux environment and using programming languages Technical communication, team work and problem solving skills English language skills Our offer Flexibility Benefits Development Fitness Security Flexible and trust-based working hours, 30 vacation days + option for additional vacation days, mobile working, individual part-time models and programs for extended periods of absence Attractive salary, share in Advantests [. .. ]
Job am 17.06.2026 bei Neuvoo.com gefunden
Advantest Europe GmbH
Senior Digital ASIC Design Engineer Verification (m/f/d)
• Baden- Württemberg Ehningen
[. .. ] challenging technical problems, and deliver high quality results on schedule and at scale. Job Duties Responsibilities Requirements gathering and elicitation for IP Architecture development for CMOS designs [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/ cases generation with a focus on chip level Documentation of implemented functionality Support for verification methodology Collaboration with other functions Your Qualifications University degree, Diploma or BS EE Background in digital design (SOC) , ASIC [. .. ] (RTL) coding (Verilog and System-Verilog) Experience with verification methodologies and concepts Experience with standard simulation tools for digital designs Basic knowledge about UNIX or Linux environment and using programming languages Technical communication, team work and problem solving skills English language skills Our offer Flexibility Benefits Development Fitness Security Flexible and trust-based working hours, 30 vacation days + option for additional vacation days, mobile working, individual part-time models and programs for extended periods of absence Attractive salary, share in Advantests [. .. ]
Job am 17.06.2026 bei Neuvoo.com gefunden
Advantest Europe GmbH
• Baden- Württemberg Böblingen
[. .. ] problems, and deliver high quality results on schedule and at scale. Job Duties Responsibilities Requirements gathering and elicitation for devices and IP Architecture development for CMOS designs [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/ cases generation. Documentation of architecture and implemented functionality Support for floor-planning and physical design Mentoring Junior Engineers Collaboration with other functions Your Qualifications University degree, Diploma or BS EE Expert background in digital design [. .. ] and silicon development cycle Experience in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs Basic knowledge about UNIX or Linux environment and using programming languages Technical communication, team work and problem solving skills English language skills Our offer Flexibility Benefits Development Fitness Security Flexible and trust-based working hours, 30 vacation days + option for additional vacation days, mobile working, individual part-time models and programs for extended periods of absence Attractive salary, share in Advantests [. .. ]
Job am 17.06.2026 bei Neuvoo.com gefunden
Advantest Europe GmbH
Senior Digital ASIC Design Engineer Verification (m/f/d) - Böblingen
• Baden- Württemberg Böblingen
[. .. ] challenging technical problems, and deliver high quality results on schedule and at scale. Job Duties Responsibilities Requirements gathering and elicitation for IP Architecture development for CMOS designs [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/ cases generation with a focus on chip level Documentation of implemented functionality Support for verification methodology Collaboration with other functions Your Qualifications University degree, Diploma or BS EE Background in digital design (SOC) , ASIC [. .. ] (RTL) coding (Verilog and System-Verilog) Experience with verification methodologies and concepts Experience with standard simulation tools for digital designs Basic knowledge about UNIX or Linux environment and using programming languages Technical communication, team work and problem solving skills English language skills Our offer Flexibility Benefits Development Fitness Security Flexible and trust-based working hours, 30 vacation days + option for additional vacation days, mobile working, individual part-time models and programs for extended periods of absence Attractive salary, share in Advantests [. .. ]
Job am 17.06.2026 bei Neuvoo.com gefunden
Advantest Europe GmbH
• Baden- Württemberg Böblingen
[. .. ] challenging technical problems, and deliver high quality results on schedule and at scale. Job Duties Responsibilities Requirements gathering and elicitation for IP Architecture development for CMOS designs [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/ cases generation with a focus on chip level Documentation of implemented functionality Support for verification methodology Collaboration with other functions Your Qualifications University degree, Diploma or BS EE Background in digital design (SOC) , ASIC [. .. ] (RTL) coding (Verilog and System-Verilog) Experience with verification methodologies and concepts Experience with standard simulation tools for digital designs Basic knowledge about UNIX or Linux environment and using programming languages Technical communication, team work and problem solving skills English language skills Our offer Flexibility Benefits Development Fitness Security Flexible and trust-based working hours, 30 vacation days + option for additional vacation days, mobile working, individual part-time models and programs for extended periods of absence Attractive salary, share in Advantests [. .. ]
Job am 17.06.2026 bei Neuvoo.com gefunden
Advantest Europe GmbH
Wir suchen: Senior Digital ASIC Design Engineer (m/f/d)
• Baden- Württemberg Böblingen
[. .. ] technical problems, and deliver high quality results on schedule and at scale. Job Duties Responsibilities Requirements gathering and elicitation for IP Architecture development for CMOS IP designs [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/ cases generation. Documentation of implemented functionality Support for floor-planning and physical design Collaboration with other functions Your Qualifications University degree, Diploma or BS EE Background in digital design (SOC) , Application Specific Integrated Circuit [. .. ] and silicon development cycle Experience in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs Basic knowledge about UNIX or Linux environment and using programming languages Technical communication, team work and problem solving skills English language skills Our offer Flexibility Benefits Development Fitness Security Flexible and trust-based working hours, 30 vacation days + option for additional vacation days, mobile working, individual part-time models and programs for extended periods of absence Attractive salary, share in Advantests [. .. ]
Job am 17.06.2026 bei Neuvoo.com gefunden
Advantest Europe GmbH
• Baden- Württemberg Böblingen
[. .. ] keep power consumption under control, solve challenging technical problems, and deliver high quality results on schedule and at scale. Job Duties Responsibilities Architecture development for CMOS designs [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/ cases generation. Documentation of implemented functionality Constraint generation and synthesis of IP blocks and the chip top level Analysis of timing and power consumption Support for floor-planning and physical design Close collaboration with design [. .. ] cycle Experience in Register Transfer Level (RTL) coding (Verilog and System Verilog) Experience with standard simulation tools for digital designs Basic knowledge about UNIX or Linux environment and using programming languages Technical communication, team work and problem solving skills English language skills Our offer Flexibility Benefits Development Fitness Security Flexible and trust-based working hours, 30 vacation days + option for additional vacation days, mobile working, individual part-time models and programs for extended periods of absence Attractive salary, share in Advantests [. .. ]
Job am 17.06.2026 bei Neuvoo.com gefunden
Advantest Europe GmbH
Gesucht: Expert Digital ASIC Design Engineer (m/f/d)
• Baden- Württemberg Böblingen
[. .. ] problems, and deliver high quality results on schedule and at scale. Job Duties Responsibilities Requirements gathering and elicitation for devices and IP Architecture development for CMOS designs [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/ cases generation. Documentation of architecture and implemented functionality Support for floor-planning and physical design Mentoring Junior Engineers Collaboration with other functions Your Qualifications University degree, Diploma or BS EE Expert background in digital design [. .. ] and silicon development cycle Experience in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs Basic knowledge about UNIX or Linux environment and using programming languages Technical communication, team work and problem solving skills English language skills Our offer Flexibility Benefits Development Fitness Security Flexible and trust-based working hours, 30 vacation days + option for additional vacation days, mobile working, individual part-time models and programs for extended periods of absence Attractive salary, share in Advantests [. .. ]
Job am 17.06.2026 bei Neuvoo.com gefunden
Advantest Europe GmbH
Senior Digital ASIC Design Engineer Synthesis (m/f/d)
• Baden- Württemberg Holzgerlingen
[. .. ] keep power consumption under control, solve challenging technical problems, and deliver high quality results on schedule and at scale. Job Duties Responsibilities Architecture development for CMOS designs [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/ cases generation. Documentation of implemented functionality Constraint generation and synthesis of IP blocks and the chip top level Analysis of timing and power consumption Support for floor-planning and physical design Close collaboration with design [. .. ] cycle Experience in Register Transfer Level (RTL) coding (Verilog and System Verilog) Experience with standard simulation tools for digital designs Basic knowledge about UNIX or Linux environment and using programming languages Technical communication, team work and problem solving skills English language skills Our offer Flexibility Benefits Development Fitness Security Flexible and trust-based working hours, 30 vacation days + option for additional vacation days, mobile working, individual part-time models and programs for extended periods of absence Attractive salary, share in Advantests [. .. ]
Job am 17.06.2026 bei Neuvoo.com gefunden
Advantest Europe GmbH
Expert Digital ASIC Design Engineer (m/f/d) - Böblingen
• Baden- Württemberg Böblingen
[. .. ] problems, and deliver high quality results on schedule and at scale. Job Duties Responsibilities Requirements gathering and elicitation for devices and IP Architecture development for CMOS designs [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/ cases generation. Documentation of architecture and implemented functionality Support for floor-planning and physical design Mentoring Junior Engineers Collaboration with other functions Your Qualifications University degree, Diploma or BS EE Expert background in digital design [. .. ] and silicon development cycle Experience in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs Basic knowledge about UNIX or Linux environment and using programming languages Technical communication, team work and problem solving skills English language skills Our offer Flexibility Benefits Development Fitness Security Flexible and trust-based working hours, 30 vacation days + option for additional vacation days, mobile working, individual part-time models and programs for extended periods of absence Attractive salary, share in Advantests [. .. ]
Job am 17.06.2026 bei Neuvoo.com gefunden
Advantest Europe GmbH
Senior Digital ASIC Design Engineer Synthesis (m/f/d) - Böblingen
• Baden- Württemberg Böblingen
[. .. ] keep power consumption under control, solve challenging technical problems, and deliver high quality results on schedule and at scale. Job Duties Responsibilities Architecture development for CMOS designs [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/ cases generation. Documentation of implemented functionality Constraint generation and synthesis of IP blocks and the chip top level Analysis of timing and power consumption Support for floor-planning and physical design Close collaboration with design [. .. ] cycle Experience in Register Transfer Level (RTL) coding (Verilog and System Verilog) Experience with standard simulation tools for digital designs Basic knowledge about UNIX or Linux environment and using programming languages Technical communication, team work and problem solving skills English language skills Our offer Flexibility Benefits Development Fitness Security Flexible and trust-based working hours, 30 vacation days + option for additional vacation days, mobile working, individual part-time models and programs for extended periods of absence Attractive salary, share in Advantests [. .. ]
Job am 17.06.2026 bei Neuvoo.com gefunden
Advantest Europe GmbH
Expert Digital ASIC Design Engineer (m/f/d)
• Baden- Württemberg Magstadt
[. .. ] problems, and deliver high quality results on schedule and at scale. Job Duties Responsibilities Requirements gathering and elicitation for devices and IP Architecture development for CMOS designs [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/ cases generation. Documentation of architecture and implemented functionality Support for floor-planning and physical design Mentoring Junior Engineers Collaboration with other functions Your Qualifications University degree, Diploma or BS EE Expert background in digital design [. .. ] and silicon development cycle Experience in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs Basic knowledge about UNIX or Linux environment and using programming languages Technical communication, team work and problem solving skills English language skills Our offer Flexibility Benefits Development Fitness Security Flexible and trust-based working hours, 30 vacation days + option for additional vacation days, mobile working, individual part-time models and programs for extended periods of absence Attractive salary, share in Advantests [. .. ]
Job am 17.06.2026 bei Neuvoo.com gefunden
Advantest Europe GmbH
Gesucht: Senior Digital ASIC Design Engineer Verification (m/f/d)
• Baden- Württemberg Böblingen
[. .. ] challenging technical problems, and deliver high quality results on schedule and at scale. Job Duties Responsibilities Requirements gathering and elicitation for IP Architecture development for CMOS designs [...]
MEHR INFOS ZUM STELLENANGEBOT
[...] Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/ cases generation with a focus on chip level Documentation of implemented functionality Support for verification methodology Collaboration with other functions Your Qualifications University degree, Diploma or BS EE Background in digital design (SOC) , ASIC [. .. ] (RTL) coding (Verilog and System-Verilog) Experience with verification methodologies and concepts Experience with standard simulation tools for digital designs Basic knowledge about UNIX or Linux environment and using programming languages Technical communication, team work and problem solving skills English language skills Our offer Flexibility Benefits Development Fitness Security Flexible and trust-based working hours, 30 vacation days + option for additional vacation days, mobile working, individual part-time models and programs for extended periods of absence Attractive salary, share in Advantests [. .. ]
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Häufig gestellte Fragen
Wieviele offene Stellenangebote gibt es für Coding Languages Jobs bei unserer Jobsuche?
Aktuell gibt es auf JobRobot 101 offene Stellenanzeigen für Coding Languages Jobs.
Wieviele Unternehmen suchen nach Bewerbern für Coding Languages Jobs?
Aktuell suchen 12 Unternehmen nach Bewerbern für Coding Languages Jobs.
Welche Unternehmen suchen nach Bewerbern für Coding Languages Stellenangebote?
Aktuell suchen zum Beispiel folgende Unternehmen nach Bewerbern für Coding Languages Stellenangebote:
- Advantest Europe GmbH (86 Jobs)
- Turing (3 Jobs)
- Fraunhofer IIS (2 Jobs)
- 12K Media (2 Jobs)
- Bosch Gruppe (1 Job)
- International Atomic Energy Agency (1 Job)
- Magna International (1 Job)
In welchen Bundesländern werden die meisten Coding Languages Jobs angeboten?
Die meisten Stellenanzeigen für Coding Languages Jobs werden derzeit in Baden-Württemberg (80 Jobs), Berlin (3 Jobs) und Bayern (2 Jobs) angeboten.
